1. Field of the Invention
The present invention relates to radio frequency communications systems, and more particularly to a novel system and method for reducing non-linearities in a Receive Signal Strength Indicator (RSSI) of a radio frequency system receiver.
2. Description of the Related Art
With the dramatic advances of deep submicron CMOS technology, the ability to integrate more and more radio functions into one piece of silicon is becoming possible. Radio functions within integrated circuits are generally partitioned into either an RF (radio frequency) chip and an IF (intermediate frequency) chip, or are partitioned into independent transmitter and receiver chips. Traditionally, RF and IF chips have been implemented in a BiCMOS, Bipolar, or Gallium Arsenide (GA) technology. However, more recently, these functions are being implemented with CMOS technology.
FIG. 1 schematically illustrates a typical prior art IF receiver system. As shown, the typical prior art IF receiver system comprises a mixer 10 and an oscillator 12 to down convert the differential RF input signal to an IF signal, a bandpass filter 14, an IF amplifier section 16, a second bandpass filter 18, a limiter 20, and an RSSI (Receive Signal Strength Indicator) circuit 22 that ranges over the entire IF input signal range.
The mixer 10 and oscillator circuit 12 in the IF system operate to first down convert the RF signal to an IF signal. The bandpass channel filter 14 then filters the IF signal to remove any unwanted mixing products. This signal is typically extremely small and can range from -100 dBm to 0 dBm, where dBm=10*log{P(mW)/1 mW}. The IF amplifier 16 amplifies the IF signal, and the amplified IF signal is then filtered by the bandpass filter 18. The signal output from the bandpass filter 18 is then provided to a very high gain limiter circuit 20. The gain limiter circuit outputs a voltage limited signal similar to a square wave. The voltage limited square wave signal is then sent to a baseband circuit (not shown) that converts the data bits into digital levels.
The IF system also implements a receive signal strength indicator function that outputs a linear signal over the entire receive input power range. This functionality is implemented by RSSI circuit 22. Since the input power range is extremely wide and digital baseband chips have a limited power supply range, the RSSI function is required to be logarithmic.
FIG. 2 is a more detailed block diagram schematically illustrating the prior art architecture for the IF amplifier 16, limiter 20, and RSSI circuit 22. FIG. 2 also illustrates the manner in which the bandpass filter 18 is interposed between the amplifier and limiter stages. FIG. 2 finally depicts the manner in which the RSSI circuitry is integrated over the entire signal path, from the IF amplifier inputs to the limiter outputs.
The IF amplifier section is represented with "Mm" gain stages labeled IF1, IF2, . . . IFm. Likewise, the limiter section is represented with "n" gain stages, labeled L1, L2, L3, L4, . . . Ln. The basic operation of the RSSI circuit 22 is to perform a full wave rectification and current limit function at each IF amplifier gain and limiter stage. The RSSI circuit 22 creates a piecewise linear logarithmic function with respect to changes in input power, and the RSSI.sub.-- OUT node is typically terminated into a resistive load to create a linear output voltage. The blocks labeled R1f, R2f, through Rmf each represent identically configured full wave current rectification circuit for each of the IF amplifier stages, and the blocks labeled R1, R2, R3, R4, through Rn each represent an identically configured full wave rectification circuit for each limiter gain stage.
The prior art circuit of FIG. 2 works quite well and is extremely linear when the intermediate bandpass filter is lossless. Many IF systems, however, require that the intermediate filter have some attenuation in order to stabilize the receiver. This attenuation can create many problems for the RSSI function. For example, variances in the attenuation can create changes in the relationship between input power and RSSI output and changes in the overall operating range, thereby deleteriously affecting the RSSI consistency and linearity.